Cadence Supports VEDA IIT by providing their full suite of EDA tools which are very much used in VLSI Design Frontend flow.

Verilog-XL, NC-Verilog are the tools from Cadence for simulating the Verilog codes and verifying the results. Ambit Compiler, Get2Chip are the tools from Cadence for performing ASIC Synthesis. Conformal from Cadence is used for doing Formal verification. Also we had a complete suite of Verisity (acquired by Cadence) for Linting and Code Coverage.

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Synopsys supports VEDA IIT by providing the cutting edge tools for Verification, Synthesis, Timing Analysis, DFT and Simulations.

VEDA is the only industry standard tool for simulating designs with Openvera verification environment. We are using this tool for our own Verification IPs.
Design Compiler from synopsys is used to perform ASIC Synthesis. Primetime from Synopsys is used for perfoming Static Timing Analysis. DFT Compiler from Synopsys is used for Scan Insertion. Formality is used for Formal Verifcation.

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Synplicity supports VEDA IIT by providing their FPGA Synthesis tool. This tool is used for FPGA Synthesis.

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